1. Field
Embodiments of the present invention generally relate to the field of semi-conductor processing, and more particularly to etching of logic gates.
2. Description of the Related Art
Ultra-large-scale integrated (ULSI) circuits may include more than one million electronic devices (e.g., transistors) that are formed on a semiconductor substrate, such as a silicon (Si) substrate, and cooperate to perform various functions within the device. Typically, the transistors used in the ULSI circuits are complementary metal-oxide-semiconductor (CMOS) field effect transistors. In one common application, CMOS transistors may be arranged to form CMOS logic gates. CMOS logic applications use a combination of p-type metal-oxide-semiconductor field-effect transistors (PMOS) and n-type metal-oxide-semiconductor field-effect transistors (NMOS).
The NMOS and PMOS transistors typically include a source region, a drain region, and a channel region between the source and drain. In the PMOS transistor, a gate structure including a polysilicon gate electrode may be disposed above the channel region and separated therefrom by a gate dielectric to control conduction between the source and drain. In the NMOS transistor, a gate structure including a polysilicon on metal gate electrode may be disposed above the channel region and separated therefrom by a high-k gate dielectric to control conduction between the source and drain.
To fabricate a CMOS logic gate as described above, the PMOS and NMOS structures may be simultaneously formed on a substrate. However, etching the dual NMOS/PMOS structures presents a difficulty in stopping the etch process on the thin gate dielectric layer of the PMOS structure during the NMOS poly/metal/hi-k gate etching while maintaining a similar feature profile between the NMOS and PMOS structures due to the exposure of the PMOS structure to the polysilicon/metal gate etch chemistries followed by the high-k gate dielectric etch for the NMOS structure. In addition, maintaining a continuous feature profile at the NMOS polysilicon/metal interface also becomes a challenge due to the etch chemistries involved.
Therefore a need exists for an improved method of fabricating CMOS logic gate structures.